This invention relates to a dual edge-triggered circuit, and more particularly to an explicit pulse generator circuit.
Dual edge-triggered circuits latch data on both the rising and falling edges of the clock. This may halve the clock frequency for the same data throughput. Since the power dissipation may be proportional to the frequency of operation, the total used power may be reduced. Further, since a significant portion of the total power of the circuit may be consumed in the clock distribution network, it may be advantageous to employ chips that operate on both edges of the clock. Thus, replacing conventional single edge-triggered circuits with dual edge-triggered circuit may result in up to 50% power savings in the clock distribution. However, the circuits must be designed in an energy-efficient manner to provide meaningful reduction in the total power consumption.
Prior art designs on creating dual edge-triggered flip-flops have been provided by replicating the latch elements of a single edge-triggered flip-flop and multiplexing the outputs. For example, M. Afghahi and J. Yuan, in xe2x80x9cDouble Edge-Triggered D-Flip-Flops for High-Speed CMOS Circuitsxe2x80x9d, IEEE Journal of Solid-State Circuits, pages 1168-1170, Vol. 26, No. 8, August 1991, suggest reducing the power dissipation of a clock distribution circuit by using flip-flops triggered on both edges of the clock pulses instead of on only one edge. The dual edge-triggered flip-flop is created from two true single-phase clock elements and a NAND gate. A. Gago et. al., in xe2x80x9cReduced implementation of D-type DET Flip-Flopsxe2x80x9d, IEEE Journal of Solid-State Circuits, pages 400-402, Vol. 28, No. 3, March 1993, present a dual edge-triggered static master-slave flip-flop. The design duplicates a single edge-triggered flip-flop but shares the clock transistors that are common to both latches. These implementations suffer from a larger clock load at the same level of performance as a single edge-triggered flip-flop. Therefore, this may offset gain from the reduced clock frequency.
In an embodiment, flip-flop device may include a transmission gate to receive data and, in response to control signals, to pass the data, a buffer coupled to an output of the first transmission gate to save and output the data, and a dual edge triggered pulse generator. The dual edge triggered pulse generator may receive a input clock signal having a frequency and a pulse width and generate the control signals as a function of the input clock signal. The control signals may have a frequency equal to twice the input clock signal frequency. The control signals may enable the first transmission gate to pass the data for a time duration less than one-half of the input clock signal pulse width so that a slave latch for latching the data is not required.
The dual edge triggered pulse generator may include two or more inverters connected in series, each inverter to successively insert a delay into the input clock signal and to generate a delay signal, and additional transmission gates, responsive to the delay signal and coupled to said at least two inverters, where the outputs of the additional transmission gates may be coupled together. One of the transmission gates may be coupled to receive and selectively pass the input clock signal as a second output signal having a delay time less than the input clock signal pulse width. Another of the transmission gates may be coupled to receive and selectively pass inverted signal of the input clock signal as a third output signal having a delay time less than the input clock signal pulse width. The second output signal and the third output signal may combine at the transmission gate outputs to form an output clock signal having two pulses within one cycle of the input clock signal.